Smp Cache 2.0
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Smp Cache 2.0
the simulator is developed to simulate smp cache coherence problem by providing support for simulated cache blocks. there are two input files, configuration file and memory trace file. the parameters include architecture characteristics, caches, cache location, cache and memory blocks. it supports different execution modes such as step by step execution and execution of selected program step by step execution with break point. this simulator also allows user to store the selected configuration and memory trace for future use.
this is a real time simulator which is used to simulate cache coherency and have a look at the effect of allocation size, cache modification, cache memory size, cache modification and miss, cache coherency on cache coherency and memory blocks.
using trace driven simulators user can try out different configurations and get different memory configurations. this will help in studying various cache configuration and corresponding change in memory block evolution. user can also select any configuration with different parameters.
the smp cache2.0 is modeled using systemc. the software architecture of the smp cache2.0 is shown in the figure 2. the thumb2 based accelerator hardware is represented as hardware vms of systemc. the accelerator vm is created by track driven simulator. in the simulation the host thread and host processor are considered to be threads. the software architecture allows systemc to create queues. once the thread running on the host is suspended, the other threads can be entered.
the simulation engine (se) is composed of various threads. for instance, the host hardware threads will be represented as systemc threads. the smp cache2.0 simulation engine also has the rq queue threads to manage the memory transactions and steady queue threads to manage the data communications among the processors.